Senior RTL Design Engineer

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Department: Semiconductors
Project Location(s): India, UK & EU
Education: Master's Degree
Compensation: As per industry standards +


  • You will have 5 or more years of experience in logic design with the following qualifications:
  • RTL design using Verilog or SystemVerilog, assertion writing
  • Design of state machines, data paths, arbitration and clock domain crossing logic
  • Logic synthesis, timing constraints
  • Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
  • Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
  • Prior experience in 10G/100G Ethernet design is a plus