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We encourage employees to be creative, driven, and take initiative. Joining P&C, with us, you will enjoy meaningful opportunities to advance your career and opportunities to work with cutting-edge technologies. As an ambitious team of professionals operating in an exciting and global environment, we are looking for passionate, talented people who will embrace the learning opportunities, challenges, and job skills that we provide.

P&C Tech Employee Benefits

P&C is an equal opportunity provider – we provide equal opportunity to applicants and employees without regard to race, color, religion, sex, age, sexual orientation, national origin, disability etc., under applicable local laws.

Stock Options
Global Relocations
Medical Insurance
Holidays & Vacations
Sick/Casual Leaves

Positions Currently Open

Senior RTL Design Engineer
Department:
Semiconductors
Experience:
5+yrs
Location:
India
Compensation:
As per Industry Standards
Positions Currently Open:
5 Positions
Skills / Experience
  •  5+ Years of relevant work experience in developing/leading
  •  Planning, tracking, partner communication
  •  Line managing, coaching, mentoring and managing engineers/team
  •  Experience in ASIC or FPGA design flows and tools.
  •  Solid knowledge of RTL development and verification methodology employing any HDL, preferably Verilog.
  •  Familiarity with SoC design EDA tools.
  •  Knowledge of at least one scripting language such as Perl, Tcl or Shell
  •  Willing and able to perform fundamental design work e.g. code RTL, perform validation/debug
  •  Proficiency in RTL coding and RTL methodologies.
  •  Knowledge of CDC and exposure to Linting.
Send your resume to hr.eu@p-ctech.com to apply
RTL Design Engineer
Department:
Semiconductors
Experience:
1-3 years
Location:
India
Compensation:
As per Industry Standards
Positions Currently Open:
5 Positions
Skills / Experience
  •  Experience in Logic design /micro-architecture / RTL coding is a must.
  •  Must have hands-on experience with SoC design and integration for complex SoCs.
  •  Strong RTL design experience with IP designs for microcontrollers/ Microprocessors expected.
  •  Experience in Verilog
  •  Hands on experience using Verilog HDL for design
  •  Proficiency in RTL coding and RTL methodologies
  •  Planning, tracking, partner communication
  •  Verilog and SystemVerilog RTL development and debug
  •  Micro-architecture specification development and design
Send your resume to hr.eu@p-ctech.com to apply
Senior Design Verification Engineer
Department:
Semiconductors
Experience:
3-8 years
Location:
India
Compensation:
As per Industry Standards
Positions Currently Open:
5 Positions
Skills / Experience
  •  Responsible for feature list development & development of verification plan.
  •  Ability to contribute to the Development of Test Bench & Test Case Development.
  •  Responsible for writing required documentations on Testbenches and Test Plan.
  •  Can be ASIC OR SoC verification sign-off (full verification cycle) for at least 2 projects.
  •  Can be IP development for at least 2 projects.
  •  Able to own and drive product development leading a team of 2-3 junior engineers.
  •  Can be VIP development : at least fully handled 2 VIP developments
  •  Experience in high speed protocols such as USB, PCIe, SATA,AMBA is desired.
  •  Experience in system/SOC/Full chip level verification desirable
  •  Mentoring other engineers based on deep core competence and expertise
Send your resume to hr.eu@p-ctech.com to apply
Design Verification Engineer
Department:
Semiconductors
Experience:
1-3 years
Location:
India
Compensation:
As per Industry Standards
Positions Currently Open:
5 Positions
Skills / Experience
  •  1 or more years of experience in Verification with hands on in ASIC Verification, SV/UVM methodology.Should have used Object Oriented Programming in the projects worked on.
  •  Responsible for Development Of Verification Plan.
  •  Experience in SoC /IP level Verification needed.
  •  Ability to contribute to the Development of Test Bench, Test Case Development and documentation of the same.
  •  CPU verification is added advantage
  •  Writing /debugging C and assembly tests desirable
  •  Excellent RTL debugging Skills
  •  Experience in high speed protocols such as USB, PCIe, Display Port, SATA,AMBA is desired.
  •  Development of Subsystem/SoC Verification and Coverage plans.
  •  Excellent communication and report documentation skills, should be a problem solver, team player and also has the ability to operate at multi levels including senior management.
  •  Should be self motivated.
Send your resume to hr.eu@p-ctech.com to apply
Senior RTL Design Engineer
Department:
Semiconductors
Experience:
5+yrs
Location:
UK & EU
Compensation:
As per Industry Standards
Skills / Experience

You will have 5 or more years of experience in logic design with the following qualifications:

  •  RTL design using Verilog or SystemVerilog, assertion writing
  •  Design of state machines, data paths, arbitration and clock domain crossing logic
  •  Logic synthesis, timing constraints
  •  Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
  •  Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
  •  Prior experience in 10G/100G Ethernet design is a plus
Send your resume to hr.eu@p-ctech.com to apply
RTL Design Engineer
Department:
Semiconductors
Experience:
2 yrs
Location:
UK & EU
Compensation:
As per Industry Standards
Skills / Experience

You will have 2 years of experience in logic design with the following qualifications:

  •  RTL design using Verilog or SystemVerilog, assertion writing
  •  Design of state machines, data paths, arbitration and clock domain crossing logic
  •  Logic synthesis, timing constraints
  •  Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
  •  Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
  •  Prior experience in 10G/100G Ethernet design is a plus
Send your resume to hr.eu@p-ctech.com to apply
Verification Lead
Department:
Semiconductors
Experience:
9 yrs
Location:
UK & EU
Compensation:
As per Industry Standards
Skills / Experience
  •  Excellent communication and interpersonal skills
  •  9 years of experience in Verification with hands on in ASIC Verification, SV/UVM methodology
  •  Creative problem solving
  •  Team player
  •  Strong and effective presentation skills, able to operate at multiple levels including senior management
  •  Experience in SoC /IP level Verification needed
  •  CPU verification is added advantage
  •  Writing /debugging C and assembly tests desirable
  •  Excellent RTL debugging Skills
  •  Self-motivated
  •  Take ownership of problems
Send your resume to hr.eu@p-ctech.com to apply

Senior RTL Design Engineer
Department:
Semiconductors
Experience:
5+yrs
Location:
UK & EU
Compensation:
As per Industry Standards
Skills / Experience

You will have 5 or more years of experience in logic design with the following qualifications:

  •  RTL design using Verilog or SystemVerilog, assertion writing
  •  Design of state machines, data paths, arbitration and clock domain crossing logic
  •  Logic synthesis, timing constraints
  •  Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
  •  Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
  •  Prior experience in 10G/100G Ethernet design is a plus
Send your resume to hr.eu@p-ctech.com to apply

RTL Design Engineer
Department:
Semiconductors
Experience:
3+yrs
Location:
India, UK & EU
Compensation:
As per Industry Standards
Skills / Experience

You will have 3 or more years of experience in logic design with the following qualifications:

  •  RTL design using Verilog or SystemVerilog, assertion writing
  •  Design of state machines, data paths, arbitration and clock domain crossing logic
  •  Logic synthesis, timing constraints
  •  Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
  •  Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
  •  Prior experience in 10G/100G Ethernet design is a plus
Send your resume to hr.eu@p-ctech.com to apply

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